The present invention relates to a method for manufacturing a MOS (CMOS) type semiconductor device, and more particularly to a method for manufacturing a CMOS type semiconductor device which includes an improved method for forming a contact hole and a wiring layer.
In the manufacture of semiconductor devices, it is necessary to decrease the contact hole size for the wiring layer so that the semiconductor devices may be miniaturized in order to accomplish high speed operations and high packing densities.
When the contact hole size decreases, the depth of an element in the device does not always decrease in the same proportion. In general, it is necessary to form a deep contact hole because the ratio between the thickness of the insulation layer in the contact hole region and the contact hole size becomes large as the semiconductor device is miniaturized. After the deep contact hole is formed, the wiring layer is formed by depositing metal on the deep contact hole. Often the wiring layer formed in the contact hole region is thinner than in the surrounding regions and the reliability of the wiring layer is decreased.
In Japanese Patent Publication No. 58-4817, the connection between the wiring layer and a semiconductor substrate in the contact hole is improved by forming a wide opening portion at the upper part of the contact hole. Specifically, as shown in FIG. 1, a phospho-silicate glass (PSG) layer 3 used as a low temperature melt insulation layer is provided on an insulation layer 2 formed on a semiconductor substrate 1, a contact hole 4 is opened, the PSG 3 is melted by heating the substrate 1 to a high temperature and a wider opening portion at the upper part of the contact hole is formed. An N type diffusion region 5 is formed in the substrate 1 as shown in FIG. 1. In general, a boron doped phospho-silicate glass (BPSG) may be used as a passivation layer in place of the PSG layer.
However, when this method is applied to CMOS type semiconductor devices, the surface impurity concentration of the N or P type diffusion regions in the semiconductor substrate decreases and the contact resistance between the wiring layer and the diffusion regions increases for the following reasons:
(1) The phosphorus included in the PSG as an impurity diffuses into the P-type diffusion region during the high temperature step;
(2) N-type impurity in the N-type diffusion region diffuses into the P-type diffusion region or P-type impurity in the P-type diffusion region diffuses into the N-type diffusion region; and
(3) The boron included in the BPSG as an impurity diffuses into the N-type diffusion region during the high temperature step.